October&2012
&–&December&2014
PRODUCTION DATA.&
机械数据 (封装 | 引脚)
8 Detailed Description<h3 id="SLUSAW5 OverviewThe bq24196 is an I2C controlled power path management device and a single cell Li-Ion battery charger. It integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and BATFET (Q4) between system and battery. The device also integrates the bootstrap diode for the high-side gate drive. <h3 id="SLUSAW5 Functional Block Diagram<h3 id="SLUSAW5 Feature Description<h4 id="SLUSAW5.1 Device Power Up<h4 id="SLUSAW5.1.1 Power-On-Reset (POR) The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR. <h4 id="SLUSAW5.1.2 Power Up from Battery without DC Source If only battery is present and the voltage is above depletion threshold (VBAT_DEPL), the BATFET turns on and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDSON in BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. The device always monitors the discharge current through BATFET. When the system is overloaded or shorted, the device will immediately turn off BATFET and keep BATFET off until the input source plugs in again. <h4 id="SLUSAW5.1.2.1 BATFET Turn Off The BATFET can be forced off by the host through I2C REG07[5]. This bit allows the user to independently turn off the BATFET when the battery condition becomes abnormal during charging. When BATFET is off, there is no path to charge or discharge the battery. When battery is not attached, the BATFET should be turned off by setting REG07[5] to 1 to disable charging and supplement mode.<h4 id="SLUSAW5.1.2.2 Shipping Mode When end equipment is assembled, the system is connected to battery through BATFET. There will be a small leakage current to discharge the battery even when the system is powered off. In order to extend the battery life during shipping and storage, the device can turn off BATFET so that the system voltage is zero to minimize the leakage. In order to keep BATFET off during shipping mode, the host has to disable the watchdog timer (REG05[5:4] = 00) and disable BATFET (REG07[5] = 1) at the same time. Once the BATFET is disabled, the BATFET can be turned on by plugging in adapter.<h4 id="SLUSAW5.1.3 Power Up from DC Source When the DC source plugs in, the bq24196 checks the input source voltage to turn on REGN LDO and all the bias circuits. It also checks the input current limit before starts the buck converter. <h4 id="SLUSAW5.1.3.1 REGN LDO The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also provides bias rail to TS1/TS2 external resistors. The pull-up rail of STAT and PGcan be connected to REGN as well. The REGN is enabled when all the conditions are valid. VBUS above UVLOZVBUS above battery + VSLEEPZ in buck mode or VBUS below battery + VSLEEPZ in boost modeAfter typical 220ms delay (100ms minimum) is completeIf one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than 50 &A from VBUS during HIZ state. The battery powers up the system when the device is in HIZ. <h4 id="SLUSAW5.1.3.2 Input Source Qualification After REGN LDO powers up, the bq24196 checks the current capability of the input source. The input source has to meet the following requirements to start the buck converter. VBUS voltage below 18 V (not in ACOV) VBUS voltage above 3.8 V when pulling 30 mA (poor source detection) Once the input source passes all the conditions above, the status register REG08[2] goes high and the PG pin goes low. An INT is asserted to the host. If the device fails the poor source detection, it will repeat the detection every 2 seconds. <h4 id="SLUSAW5.1.3.3 Input Current Limit Detection The USB ports on personal computers are convenient charging source for portable devices (PDs). If the portable device is attached to a USB host, the USB specification requires the portable device to draw limited current (100 mA/500 mA in USB 2.0, and 150 mA/900 mA in USB 3.0). If the portable device is attached to a charging port, it is allowed to draw up to 1.5 A. After the PG is LOW or REG08[2] goes HIGH, the charger device always runs input current limit detection when a DC source plugs in unless the charger is in HIZ during host mode. The bq24196 sets input current limit through PSEL and OTG pins. After the input current limit detection is done, the host can write to REG00[2:0] to change the input current limit. <h4 id="SLUSAW5.1.3.4 PSEL/OTG Pins Set Input Current Limit The bq24196 has PSEL. It directly takes the USB PHY device output to decide whether the input is USB host or charging port. Table 2. bq24196 Input Current Limit DetectionPSELOTGINPUT CURRENT LIMITREG08[7:6]HIGHLOW100 mA01HIGHHIGH500 mA01LOW&3 A10<h4 id="SLUSAW5.1.3.5 HIZ State wth 100mA USB HostIn battery charging spec, the good battery threshold is the minimum charge level of a battery to power up the portable device successfully. When the input source is 100-mA USB host, and the battery is above bat-good threshold (VBATGD), the device follows battery charging spec and enters high impedance state (HIZ). In HIZ state, the device is in the lowest quiescent state with REGN LDO and the bias circuits off. The charger device sets REG00[7] to 1, and the VBUS current during HIZ state will be less than 30 &A. The system is supplied by the battery. Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7] = 0. When the processor host wakes up, it is recommended to first check if the charger is in HIZ state. In default mode, the charger IC will reset REG00[7] back to 0 when input source is removed. When another source plugs in, the charger IC will run detection again, and update the input current limit. <h4 id="SLUSAW.1.3.6 Force Input Current Limit DetectionThe host can force the charger device to run input current limit detection by setting REG07[7] = 1. After the detection is complete, REG07[7] will return to 0 by itself. <h4 id="SLUSAW5.1.4 Converter Power-UpAfter the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery. The bq24196 provides soft-start when ramp up the system rail. When the system rail is below 2.2 V, the input current limit is forced to 100 mA. After the system rises above 2.2 V, the charger device sets the input current limit set by the lower value between register and ILIM pin. As a battery charger, the bq24196 deploys a 1.5-MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design. A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage. In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS. <h4 id="SLUSAW5.1.5 Boost Mode Operation from BatteryThe bq24196 supports boost converter operation to deliver power from the battery to other portable devices through USB port. The boost mode output current rating meets the USB On-The-Go 500-mA output requirement. The maximum output current is 1.3 A. The boost operation can be enabled if the following conditions are valid:BAT above BATLOWV threshold (VBATLOWV set by REG04[1])VBUS less than BAT+VSLEEP (in sleep mode)Boost mode operation is enabled (OTG pin HIGH and REG01[5:4] = 10)After 220-ms delay from boost mode enableIn boost mode, the bq24196 employs a 1.5-MHz step-up switching regulator. Similar to buck operation, the device switches from PWM operation to PFM operation at light load to improve efficiency. During boost mode, the status register REG08[7:6] is set to 11, the VBUS output is 5 V and the output current can reach up to 500 mA or 1.3 A, selected via I2C (REG01[0]). Any fault during boost operation, including VBUS over-voltage or over-current, sets the fault register REG09[6] to 1 and an INT is asserted. <h4 id="SLUSAW5.2 Power Path ManagementThe bq24196 accommodates a wide range of input sources from USB, wall adapter, to car battery. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both. <h4 id="SLUSAW5.2.1 Narrow VDC ArchitectureThe device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above the minimum system voltage (default 3.5 V). When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is 150 mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET. When the battery charging is disabled or terminated, the system is always regulated at 150 mV above the minimum system voltage setting. The status register REG08[0] goes high when the system is in minimum system voltage regulation.Figure 10. V(SYS) vs V(BAT)<h4 id="SLUSAW5.2.2 Dynamic Power ManagementTo meet maximum current limit in USB spec and avoid over loading the adapter, the bq24196 features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage.When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit. When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery. During DPM mode (either VINDPM or IINDPM), the status register REG08[3] will go high.
shows the DPM response with 9-V/1.2-A adapter, 3.2-V battery, 2.8-A charge current and 3.4-V minimum system voltage setting. Figure 11. DPM Response<h4 id="SLUSAW5.2.3 Supplement ModeWhen the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30 mV when the current is low. This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current.
shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold.Figure 12. BATFET V-I Curve<h4 id="SLUSAW5.3 Battery Charging ManagementThe bq24196 charges 1-cell Li-Ion battery with up to 2.5A charge current for high capacity tablet battery. The 12-m&O BATFET improves charging efficiency and minimizes the voltage drop during discharging. <h4 id="SLUSAW5.3.1 Autonomous Charging CycleWith battery charging enabled at POR (REG01[5:4] = 01), the bq24196 can complete a charging cycle without host involvement. The device default charging parameters are listed in . Table 3. Charging Parameter Default SettingDEFAULT MODEbq24196Charging voltage4.208 VCharging current2.048 APre-charge current256 mATermination current256 mATemperature profileHot/ColdSafety timer8 hoursA new charge cycle starts when the following conditions are valid:Converter startsBattery charging is enabled by I2C register bit (REG01[5:4]) = 01 and CE is lowNo thermistor fault on TS1 and TS2No safety timer faultBATFET is not forced to turn off (REG07[5])The charger device automatically terminates the charging cycle when the charging current is below termination threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below recharge threshold (REG04[0]), the bq24196 automatically starts another charging cycle.The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is complete, an INT is asserted to notify the host.The host can always control the charging operation and optimize the charging parameters by writing to the registers through I2C. <h4 id="SLUSAW.3.2 Battery Charging Profile The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the beginning of a charging cycle, the device checks the battery voltage and applies current. Table 4. Charging Current SettingVBATCHARGING CURRENTREG DEFAULT SETTINGREG08[5:4]& 2 V100 mA&012 V - 3 VREG03[7:4]256 mA01& 3 VREG02[7:2]2048 mA10If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate. Figure 13. Battery Charging Profile<h4 id="SLUSAW5.3.3 Thermistor Cold/Hot Temperature WindowThe bq24196 continuously monitors battery temperature by measuring the voltage between the TS pins and ground, typically determined by a negative temperature coefficient thermistor and an external voltage divider. The device compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. During the charge cycle the battery temperature must be within the VLTF to VTCO thresholds, else the device suspends charging and waits until the battery temperature is within the VLTF to VHTF range. Figure 14. TS Resistor NetworkWhen the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT is asserted to the host. The STAT pin indicates the fault when charging is suspended.Figure 15. TS Pin Thermistor Sense ThresholdsAssuming a 103AT NTC thermistor is used on the battery pack, the value RT1 and RT2 can be determined by using the following equations:Equation 1. Select 0&C to 45&C range for Li-ion or Li-polymer battery,
RTHCOLD = 27.28 k&O
RTHHOT = 4.911 k&O
RT1 = 5.52 k&O
RT2 = 31.23 k&O <h4 id="SLUSAW5.3.4 Charging TerminationThe bq24196 terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn back on to engage supplement mode. When termination occurs, the status register REG08[5:4] is 11, and an INT is asserted to the host. Termination is temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination can be disabled by writing 0 to REG05[7].<h4 id="SLUSAW5.3.4.1 Termination when REG02[0] = 1When REG02[0] is HIGH to reduce the charging current by 80%, the charging current could be less than the termination current. The charger device termination function should be disabled. When the battery is charged to fully capacity, the host disables charging through CE pin or REG01[5:4]. <h4 id="SLUSAW5.3.4.2 Termination when REG05[6] = 1Usually the STAT bit indicates charging complete when the charging current falls below termination threshold. Write REG05[6] = 1 to enable an early &charge done& indication on STAT pin. The STAT pin goes high when the charge current reduces below 800 mA. The charging cycle is still on-going until the current falls below the termination threshold. <h4 id="SLUSAW5.3.5 Charging Safety TimerThe bq24196 has safety timer to prevent extended charging cycle due to abnormal battery conditions. In default mode, the device keeps charging the battery with 5-hour fast charging safety timer regardless of REG05[2:1] default value. At the end of the 5 hours, the EN_HIZ (REG00[7]) is set to signal the buck converter stops and the system load is supplied by the battery. The EN_HIZ bit can be cleared to restart the buck converter. In host mode, the device keeps charging the battery until the fast charging safety timer expired. The duration of safety timer can be set by the REG05[2:1] bits (default = 8 hours). At the end of safety timer, the EN_HIZ (REG00[7]) is cleared to signal the buck converter continues to operation to supply system load.The safety timer is 1 hour when the battery is below BATLOWV threshold. The user can program fast charge safety timer through I2C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C (REG05[3]). The following actions restart the safety timer:At the beginning of a new charging cycleToggle the CE pin HIGH to LOW to HIGH (charge enable)Write REG01[5:4] from 00 to 01 (charge enable)Write REG05[3] from 0 to 1 (safety timer enable)During input voltage/current regulation or thermal regulation, or when FORCE_20PCT (REG02[0]) bit is set, the safety timer counts at half clock rate since the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to REG07[6]. It is recommended to disable safety timer first by clearing REG05[3] bit before safety timer configuration is changed. The safety timer should be re-enabled by setting REG05[3] bit.<h4 id="SLUSAW.3.6 USB Timer when Charging from USB100mA SourceThe total charging time in default mode from USB100-mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ. <h4 id="SLUSAW5.4 Status Outputs (PG, STAT, and INT)<h4 id="SLUSAW5.4.1 Power Good Indicator (PG)In bq24196, PG goes LOW to indicate a good input source when:VBUS above UVLOVBUS above battery (not in sleep)VBUS below ACOV threshold VBUS above 3.8 V when 30-mA current is applied (not a poor source)<h4 id="SLUSAW5.4.2 Charging Status Indicator (STAT)The bq24196 indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application diagram shows. Table 5. STAT Pin State CHARGING STATESTATCharging in progress (including recharge)LOWCharging completeHIGHSleep mode, charge disableHIGHCharge suspend (Input over-voltage, TS fault, timer fault, input or system over-voltage)blinking at 1Hz <h4 id="SLUSAW5.4.3 Interrupt to Host (INT)In some applications, the host does not always monitor the charger operation. The INT notifies the system on the device operation. The following events will generate 256-us INT pulse. USB/adapter source identified (through PSEL and OTG pins)Good input source detectedVVBUS - VBAT & VSLEEPZVVBUS & VACOVcurrent limit above IBADSRCInput removedCharge CompleteAny FAULT event in REG09When a fault occurs, the charger device sends out INT and keeps the fault state in REG09 until the host reads the fault register. Before the host reads REG09 and all the faults are cleared, the charger device would not send any INT upon new faults. In order to read the current fault status, the host has to read REG09 two times consecutively. The 1st reads fault register status from the last read and the 2nd reads the current fault register status. <h4 id="SLUSAW5.5 Protections<h4 id="SLUSAW5.5.1 Input Current Limit on ILIMFor safe operation, the bq24196 has an additional hardware pin on ILIM to limit maximum input current on ILIM pin. The input maximum current is set by a resistor from ILIM pin to ground as: Equation 2. The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For example, if the register setting is 111 for 3 A, and ILIM has a 353-&O resistor to ground for 1.5 A, the input current limit is 1.5 A. ILIM pin can be used to set the input current limit rather than the register settings. The device regulates ILIM pin at 1 V. If ILIM voltage exceeds 1 V, the device enters input current regulation (Refer to Dynamic Power Path Management section). The voltage on the ILIM pin is proportional to the input current. The ILIM pin can be used to monitor the input current per :Equation 3. For example, if the ILIM pin sets 2 A, and the ILIM voltage is 0.6 V, the actual input current is 1.2 A. If the ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 1 V. If the ILIM pin is short, the input current limit is set by the register. <h4 id="SLUSAW5.5.2 Thermal Regulation and Thermal ShutdownThe bq24196 monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]), the device lowers down the charge current. The wide thermal regulation range from 60&C to 120&C allows the user to optimize the system thermal performance. During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1] goes high. Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and an INT is asserted to the host. <h4 id="SLUSAW5.5.3 Voltage and Current Monitoring in Buck ModeThe bq24196 closely monitor the input and system voltage, as well as HSFET and LSFET current for safe buck mode operation. <h4 id="SLUSAW5.5.3.1 Input Over-Voltage (ACOV)The maximum input voltage for buck mode operation is 18 V. If VBUS voltage exceeds 18 V, the device stops switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An INT is asserted to the host.<h4 id="SLUSAW5.5.3.2 System Over-Voltage Protection (SYSOVP)The charger device monitors the voltage at SYS. When system over-voltage is detected, the converter is stopped to protect components connected to SYS from high voltage damage. <h4 id="SLUSAW.5.4 Voltage and Current Monitoring in Boost ModeThe bq24196 closely monitors the VBUS voltage, as well as HSFET and LSFET current to ensure safe boost mode operation. <h4 id="SLUSAW5.5.4.1 VBUS Over-Voltage Protection The boost mode regulated output is 5 V. When an adapter plugs in during boost mode, the VBUS voltage will rise above regulation target. Once the VBUS voltage exceeds 5.3 V, the bq24196 stops switching and the device exits boost mode. The fault register REG09[6] is set high to indicate fault in boost operation. An INT is asserted to the host. <h4 id="SLUSAW5.5.5 Battery Protection<h4 id="SLUSAW5.5.5.1 Battery Over-Current Protection (BATOVP)The battery over-voltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charge. The fault register REG09[5] goes high and an INT is asserted to the host. <h4 id="SLUSAW5.5.5.2 Charging During Battery Short ProtectionIf the battery voltage falls below 2 V, the charge current is reduced to 100 mA for battery safety. <h4 id="SLUSAW5.5.5.3 System Over-Current Protection If the system is shorted or exceeds the over-current limit, the BATFET is latched off. DC source insertion on VBUS is required to reset the latch-off condition and turn on BATFET. <h4 id="SLUSAW.6 Serial InterfaceThe bq24196 uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave. The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits). Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pull-up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain. <h4 id="SLUSAW5.6.1 Data ValidityThe data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred. Figure 16. Bit Transfer on the I2C Bus<h4 id="SLUSAW5.6.2 START and STOP ConditionsAll transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition. Figure 17. START and STOP conditions<h4 id="SLUSAW.6.3 Byte FormatEvery byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL. Figure 18. Data Transfer on the I2C Bus<h4 id="SLUSAW5.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse. When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer. <h4 id="SLUSAW5.6.5 Slave Address and Data Direction BitAfter the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). Figure 19. Complete Data Transfer<h4 id="SLUSAW5.6.5.1 Single Read and WriteFigure 20. Single WriteFigure 21. Single ReadIf the register address is not defined, the charger IC send back NACK and go back to the idle state. <h4 id="SLUSAW5.6.5.2 Multi-Read and Multi-WriteThe charger device supports multi-read and multi-write on REG00 through REG08. Figure 22. Multi-WriteFigure 23. Multi-ReadThe fault register REG09 locks the previous fault and only clears it after the register is read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not support multi-read or multi-write. <h3 id="SLUSAW5 Device Functional Modes<h4 id="SLUSAW5.1 Host Mode and Default ModeThe bq24196 is a host controlled device, but it can operate in default mode without host management. In default mode, bq24196 can be used as an autonomous charger with no host or with host in sleep. When the charger is in default mode, REG09[7] is HIGH. When the charger is in host mode, REG09[7] is LOW. After power-on-reset, the device starts in watchdog timer expiration state, or default mode. All the registers are in the default settings. Any write command to bq24196 transitions the device from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 twice to REG01[6] before the watchdog timer expires (REG05[5:4]), or disable watchdog timer by setting REG05[5:4] = 00.Figure 24. Watchdog Timer Flow Chart<h4 id="SLUSAW5.1.1 Plug in USB100mA Source with Good BatteryWhen the input source is detected as 100-mA USB host, and the battery voltage is above batgood threshold (VBATGD), the charger device enters HIZ state to meet the battery charging spec requirement. If the charger device is in host mode, it will stay in HIZ state even after the USB100-mA source is removed, and the adapter plugs in. During the HIZ state, REG00[7] is set HIGH and the system load is supplied from battery. It is recommended that the processor host always checks if the charger IC is in HIZ state when it wakes up. The host can write REG00[7] to 0 to exit HIZ state. If the charger is in default mode, when the DC source is removed, the charger device will get out of HIZ state automatically. When the input source plugs in again, the charger IC runs detection on the input source and update the input current limit. <h4 id="SLUSAW5.1.2 USB Timer when Charging from USB 100-mA SourceThe total charging time in default mode from USB 100-mA source is limited by a 45-min max timer. At the end of the timer, the device stops the converter and goes to HIZ. <h3 id="SLUSAW5 Register MapTable 6. Register MapREGISTER REGISTER NAMERESET REG00 Input Source Control Register , or 30REG01 Power-On Configuration Register , or 1BREG02Charge Current Control Register, or 60REG03Pre-Charge/Termination Current Control Register , or 11REG04Charge Voltage Control Register, or CAREG05Charge Termination/Timer Control Register , or 9AREG06Thermal Regulation Control Register, or 03REG07Misc Operation Control Register, or 4BREG08System Status Register&REG09Fault Register&REG0AVender / Part / Revision Status Register&<h4 id="SLUSAW5.1 I2C RegistersAddress: 6BH. REG00-07 support Read and Write. REG08-0A are read only. <h4 id="SLUSAW5.1.1 Input Source Control Register REG00 (reset = , or 30) Figure 25. REG00 Input Source Control Register Format76543210EN_HIZVINDPM[3]VINDPM[2]VINDPM[1]VINDPM[0]IINLIM[2]IINLIM[1]IINLIM[0]R/WR/WR/WR/WR/WR/WR/WR/WLEGEND: R/W = Read/W R = R -n = value after resetTable 7. REG00 Input Source Control Register DescriptionBITFIELDTYPERESETDESCRIPTIONBit 7EN_HIZR/W00 & Disable, 1 & EnableDefault: Disable (0)Input Voltage LimitBit 6VINDPM[3]R/W0640 mVOffset 3.88 V, Range: 3.88 V to 5.08 VDefault: 4.36 V (0110)Bit 5VINDPM[2]R/W1320 mVBit 4VINDPM[1]R/W1160 mVBit 3VINDPM[0]R/W080 mVInput Current Limit (Actual input current limit is the lower of I2C and ILIM)Bit 2IINLIM[2]R/W0000 & 100 mA, 001 & 150 mA, 010 & 500 mA,
011 & 900 mA, 100 & 1.2 A,
101 & 1.5 A,
110 & 2 A, 111 & 3 ADefault SDP: 100 mA (000)(OTG pin = 0) or 500 mA (010) (OTG pin = 1) Default DCP/CDP: 3 A (111)Bit 1IINLIM[1]R/W0Bit 0IINLIM[0]R/W0<h4 id="SLUSAW5.1.2 Power-On Configuration Register REG01 (reset = , or 1B)Figure 26. REG01 Power-On Configuration Register Format76543210Register ResetI2C Watchdog Timer ResetCHG_CONFIG[1]CHG_CONFIG[0]SYS_MIN[2]SYS_MIN[1]SYS_MIN[0]BOOST_LIMR/WR/WR/WR/WR/WR/WR/WR/WLEGEND: R/W = Read/W R = R -n = value after resetTable 8. REG01 Power-On Configuration Register DescriptionBITFIELDTYPERESETDESCRIPTIONNOTEBit 7Register ResetR/W00 & Keep current register setting,
1 & Reset to defaultDefault: Keep current register setting (0) Back to 0 after register resetBit 6I2C Watchdog Timer ResetR/W00 & N 1 & ResetDefault: Normal (0) Back to 0 after timer resetCharger Configuration Bit 5CHG_CONFIG[1]R/W000 & Charge Disable, 01 & Charge Battery,
10/11 & OTGDefault: Charge Battery (01)Bit 4CHG_CONFIG[0]R/W1Minimum System Voltage LimitBit 3SYS_MIN[2]R/W10.4 VOffset: 3.0 V, Range 3.0 V to 3.7 V Default: 3.5 V (101)Bit 2SYS_MIN[1]R/W00.2 VBit 1SYS_MIN[0]R/W10.1 VBoost Mode Current LimitBit 0BOOST_LIMR/W10 & 500 mA, 1 & 1.3 ADefault: 1.3 A (1)<h4 id="SLUSAW5.1.3 Charge Current Control Register REG02 (reset = , or 60)Figure 27. REG02 Charge Current Control Register Format76543210ICHG[5]ICHG[4]ICHG[3]ICHG[2]ICHG[1]ICHG[0]ReservedFORCE_20PCTR/WR/WR/WR/WR/WR/WR/WR/WLEGEND: R/W = Read/W R = R -n = value after resetTable 9. REG02 Charge Current Control Register DescriptionBITFIELDTYPERESETDESCRIPTIONNOTEFast Charge Current LimitBit 7ICHG[5]R/W02048 mAOffset: 512 mARange: 512 to 2496 mADefault: 2048 mA (011000)Bit 6ICHG[4]R/W11024 mABit 5ICHG[3]R/W1512 mABit 4ICHG[2]R/W0256 mABit 3ICHG[1]R/W0128 mABit 2ICHG[0]R/W064 mABit 1ReservedR/W00 - ReservedReserved. Must write &0&Bit 0FORCE_20PCTR/W00 - ICHG as REG02[7:2] (Fast Charge Current Limit) and REG03[7:4] (Pre-Charge Current Limit) programmed
1 - ICHG as 20% of REG02[7:2] (Fast Charge Current Limit) and 50% of REG03[7:4] (Pre-Charge Current Limit) programmedDefault: ICHG as REG02[7:2] (Fast Charge Current Limit) and REG03[7:4] (Pre-Charge Current Limit) programmed (0)<h4 id="SLUSAW5.1.4 Pre-Charge/Termination Current Control Register REG03 (reset = , or 11)Figure 28. REG03 Pre-Charge/Termination Current Control Register Format76543210IPRECHG[3]IPRECHG[2]IPRECHG[1]IPRECHG[0]ITERM[3]ITERM[2]ITERM[1]ITERM[0]R/WR/WR/WR/WR/WR/WR/WR/WLEGEND: R/W = Read/W R = R -n = value after resetTable 10. REG03 Pre-Charge/Termination Current Control Register DescriptionBITFIELDTYPERESETDESCRIPTIONNOTEPre-Charge Current LimitBit 7IPRECHG[3]R/W01024 mAOffset: 128 mA,Range: 128 mA to 2048 mA
Default: 256 mA (0001)Bit 6IPRECHG[2]R/W0512 mABit 5IPRECHG[1]R/W0256 mABit 4IPRECHG[0]R/W1128 mATermination Current LimitBit 3ITERM[3]R/W01024 mAOffset: 128 mA Range: 128 mA to 2048 mA Default: 256 mA (0001)Bit 2ITERM[2]R/W0512 mABit 1ITERM[1]R/W0256 mABit 0ITERM[0]R/W1128 mA<h4 id="SLUSAW.1.5 Charge Voltage Control Register REG04 (reset = , or CA)Figure 29. REG04 Charge Voltage Control Register Format76543210VREG[5]VREG[4]VREG[3]VREG[2]VREG[1]VREG[0]BATLOWVVRECHGR/WR/WR/WR/WR/WR/WR/WR/WLEGEND: R/W = Read/W R = R -n = value after resetTable 11. REG04 Charge Voltage Control Register DescriptionBITFIELDTYPERESETDESCRIPTIONNOTECharge Voltage LimitBit 7VREG[5]R/W1512 mVOffset: 3.504 V Range: 3.504 V to 4.400 V (111000)Default: 4.208 V (101100) Default: 4.304 V (110010) Bit 6VREG[4]R/W1256 mVBit 5VREG[3]R/W0128 mVBit 4VREG[2]R/W064 mVBit 3VREG[1]R/W132 mVBit 2VREG[0]R/W016 mVBattery Precharge to Fast Charge ThresholdBit 1BATLOWVR/W10 & 2.8 V, 1 & 3.0 VDefault: 3.0 V (1)Battery Recharge Threshold (below battery regulation voltage)Bit 0VRECHGR/W00 & 100 mV, 1 & 300 mVDefault: 100 mV (0)<h4 id="SLUSAW5.1.6 Charge Termination/Timer Control Register REG05 (reset = , or 9A)Figure 30. REG05 Charge Termination/Timer Control Register Format76543210EN_TERMTERM_STATWATCHDOG[1]WATCHDOG[0]EN_TIMERCHG_TIMER[1]CHG_TIMER[0]ReservedR/WR/WR/WR/WR/WR/WR/WR/WLEGEND: R/W = Read/W R = R -n = value after resetTable 12. REG05 Charge Termination/Timer Control Register DescriptionBITFIELDTYPERESETDESCRIPTIONNOTECharging Termination EnableBit 7EN_TERMR/W10 & Disable, 1 & EnableDefault: Enable termination (1)Termination Indicator ThresholdBit 6TERM_STATR/W00 & Match ITERM,
1 & STAT pin high before actual termination when charge current below 800 mADefault Match ITERM (0)I2C Watchdog Timer SettingBit 5WATCHDOG[1]R/W000 & Disable timer, 01 & 40 s, 10 & 80 s, 11 & 160 sDefault: 40 s (01)Bit 4WATCHDOG[0]R/W1Charging Safety Timer EnableBit 3EN_TIMERR/W10 & Disable, 1 & EnableDefault: Enable (1)Fast Charge Timer SettingBit 2CHG_TIMER[1]R/W000 & 5 hrs, 01 & 8 hrs, 10 & 12 hrs, 11 & 20 hrsDefault: 8 hours (01) (See Charging Safety Timer for details)Bit 1CHG_TIMER[0]R/W1Bit 0ReservedR/W00 - ReservedReserved. Must write &0&<h4 id="SLUSAW5.1.7 Thermal Regulation Control Register REG06 (reset = , or 03)Figure 31. REG06 Thermal Regulation Control Register Format76543210ReservedReservedReservedReservedReservedReservedTREG[1]TREG[0]R/WR/WR/WR/WR/WR/WR/WR/WLEGEND: R/W = Read/W R = R -n = value after resetTable 13. REG06 Thermal Regulation Control Register DescriptionBITFIELDTYPERESETDESCRIPTIONNOTEBit 7ReservedR/W00 - ReservedReserved. Must write &0&Bit 6ReservedR/W00 - ReservedReserved. Must write &0&Bit 5ReservedR/W00 - ReservedReserved. Must write &0&Bit 4ReservedR/W00 - ReservedReserved. Must write &0&Bit 3ReservedR/W00 - ReservedReserved. Must write &0&Bit 2ReservedR/W00 - ReservedReserved. Must write &0&Thermal Regulation ThresholdBit 1TREG[1]R/W100 & 60&C, 01 & 80&C, 10 & 100&C, 11 & 120&CDefault: 120&C (11)Bit 0TREG[0]R/W1<h4 id="SLUSAW5.1.8 Misc Operation Control Register REG07 (reset = , or 4B)Figure 32. REG07 Misc Operation Control Register Format76543210DPDM_ENTMR2X_ENBATFET_DisableReservedReservedReservedINT_MASK[1]INT_MASK[0]R/WR/WR/WR/WR/WR/WR/WR/WLEGEND: R/W = Read/W R = R -n = value after resetTable 14. REG07 Misc Operation Control Register DescriptionBITFIELDTYPERESETDESCRIPTIONNOTE Set default input current limit from PSEL/OTG pinsBit 7DPDM_ENR/W00 & Not in D+/D& 1 & Force D+/D& detectionDefault: Not in D+/D& detection (0), Back to 0 after detection completeSafety Timer Setting during Input DPM and Thermal RegulationBit 6TMR2X_ENR/W10 & Safety timer not slowed by 2X during input DPM or thermal regulation,
1 & Safety timer slowed by 2X during input DPM or thermal regulationDefault: Safety timer slowed by 2X (1)Force BATFET OffBit 5BATFET_DisableR/W00 & Allow Q4 turn on, 1 & Turn off Q4Default: Allow Q4 turn on(0)Bit 4ReservedR/W00 & ReservedBit 3ReservedR/W11 & ReservedBit 2ReservedR/W00 & ReservedBit 1INT_MASK[1]R/W10 & No INT during CHRG_FAULT, 1 & INT on CHRG_FAULTDefault: INT on CHRG_FAULT (1)Bit 0INT_MASK[0]R/W10 & No INT during BAT_FAULT, 1 & INT on BAT_FAULTDefault: INT on BAT_FAULT (1)<h4 id="SLUSAW.1.9 System Status Register REG08Figure 33. REG08 System Status Register Format76543210VBUS_STAT[1]VBUS_STAT[0]CHRG_STAT[1]CHRG_STAT[0]DPM_STATPG_STATTHERM_STATVSYS_STATRRRRRRRRLEGEND: R = R -n = value after resetTable 15. REG08 System Status Register DescriptionBITFIELDTYPEDESCRIPTIONBit 7VBUS_STAT[1]R00 & Unknown (no input, or DPDM detection incomplete), 01 & USB host, 10 & Adapter port, 11 & OTGBit 6VBUS_STAT[0]RBit 5CHRG_STAT[1]R00 & Not Charging, 01 & Pre-charge (&VBATLOWV), 10 & Fast Charging, 11 & Charge Termination DoneBit 4CHRG_STAT[0]RBit 3DPM_STATR0 & Not DPM, 1 & VINDPM or IINDPMBit 2PG_STATR0 & Not Power Good, 1 & Power GoodBit 1THERM_STATR0 & Normal, 1 & In Thermal RegulationBit 0VSYS_STATR0 & Not in VSYSMIN regulation (BAT & VSYSMIN), 1 & In VSYSMIN regulation (BAT & VSYSMIN)<h4 id="SLUSAW5.1.10 Fault Register REG09Figure 34. REG09 Fault Register Format76543210WATCHDOG_ FAULTBOOST_ FAULTCHRG_FAULT[1]CHRG_FAULT[0]BAT_FAULTNTC_FAULT[2]NTC_FAULT[1]NTC_FAULT[0]RRRRRRRRLEGEND: R = R -n = value after resetTable 16. REG09 Fault Register DescriptionBITFIELDTYPEDESCRIPTIONBit 7WATCHDOG_FAULTR0 & Normal, 1- Watchdog timer expirationBit 6BOOST_FAULTR0 & Normal, 1 & VBUS overloaded (OCP), or VBUS OVP in boost modeBit 5CHRG_FAULT[1]R00 & Normal, 01 & Input fault (VBUS OVP or VBAT & VBUS & 3.8 V), 10 - Thermal shutdown,
11 & Charge Safety Timer ExpirationBit 4CHRG_FAULT[0]RBit 3BAT_FAULTR0 & Normal, 1 & BATOVPBit 2NTC_FAULT[2]R 000 & Normal, 101 & Cold, 110 & HotBit 1NTC_FAULT[1]RBit 0NTC_FAULT[0]R<h4 id="SLUSAW5.1.11 Vender / Part / Revision Status Register REG0A (reset = , or 2B)Figure 35. REG0A Vender / Part / Revision Status Register Format76543210ReservedReservedPN[2]PN[1]PN[0]TS_PROFILEDEV_REG[0]DEV_REG[1]RRRRRRRRLEGEND: R = R -n = value after resetTable 17. REG0A Vender / Part / Revision Status Register DescriptionBITFIELDTYPERESETDESCRIPTIONBit 7ReservedR00 - ReservedBit 6ReservedR00 - ReservedDevice ConfigurationBit 5PN[2]R1101Bit 4PN[1]R0Bit 3PN[0]R1Bit 2TS_PROFILER00 - Cold/Hot windowBit 1DEV_REG[0]R111Bit 0DEV_REG[1]R1